1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device including a field effect transistor provided on a silicon substrate.
2. Related Art
There are many technologies to form silicide layer on a silicon substrate for semiconductor process. The resistance of gate electrode or source/drain is reduced by using the silicide layer. JP-A No. 2005-159336 is one of a related art to show those semiconductor processing technologies.
This document discloses a formation process of a silicide layer in a semiconductor device having an LDD (Lightly Doped Drain) structure. According to the disclosure, firstly a gate electrode and a low concentration doped region are formed on the silicon substrate, and a spacer is formed on a lateral face of the gate electrode. Then a buffer layer, constituted of an insulating layer, is formed on the silicon substrate, and dopant is implanted to form source/drain region. The buffer layer is then removed by a dry etching process. Through such process, the formation of the spacer, as well as the removal of the buffer layer, incurs an over-etching of the silicon substrate to a similar extent.
[Patented document 1] JP-A No. 2005-159336
In the foregoing process, however, the formation of the high concentration doped region is followed by the dry etching of the silicon substrate. Accordingly, despite having implanted the dopant with high concentraion to a predetermined depth, the high dose-implanted region that serves as a source/drain region becomes too shallow because the surface of the implanted region is removed through the dry etching process. On the other hand, the junction position of the high dose-implanted region remains substantially unchanged. As a result, a junction leakage current increases by substantially shallowering high concentration region under the silicide layer. Therefore, the method has a room for improvement from the viewpoint of suppressing a junction leak current of the transistor after being formed into a silicide.
In this respect, the cited document proposes a method of keeping the silicon from being scraped, in order to prevent the reduction in depth of the doped region because of the over-etching. Specifically, the etching of the insulating layer for forming the spacer is performed in two steps. A silicon nitride layer is employed as the buffer layer, and the silicon nitride layer is removed by etching after the ion implantation. Such steps, according to the cited document, prevent the silicon from being scraped, during the formation of the spacer and the removal of the buffer layer.
In the vicinity of the surface of the silicon substrate, however, dopant for forming a well or a channel region is introduced, prior to forming the source/drain region. Besides, dopant for forming a pocket region may be introduced. These dopants are of the opposite conductive type to those introduced for forming the source/drain region.
In case of preventing the surface of the silicon substrate from being scraped as shown in the cited document, the dopant of the opposite conductive type is present in the vicinity of the surface of the source/drain region, and increase the resisitivity of the source/drain region. Accordingly, the foregoing method has a room for improvement from the viewpoint of securing an effective junction depth of the source/drain region.